There exists a need in the art for a method and apparatus to reduce the data size of exceptionally large layout data structures, particularly in layout applications whereby blocks of circuitry and embedded features within an IC are represented. These layout data structures can potentially take up excessive amounts of memory space within a computer system making them difficult to manipulate. Further, the size of these layout data structures taxes the storage capacity of the computer system.
There are a number of methods in the art to reduce data size. Generally, compression systems work by removing redundant or superfluous data in order to reduce the amount of data to be compressed. These systems often trade functionality and quality for higher compression ratios. Further, compression systems in general require significant computing power.
U.S. Pat. No. 6,594,801, which issued to Dishon et al on Jul. 15, 2004, provides a method for compressing a data structure representing a layout of a multi layered VLSI device. The method comprises the steps of generating a non-functional elements locating data structure representing all the non-functional elements of all layers within the layout; deleting representations of non-functional elements from the data structure and adding the compressed non functional elements data structure to generate a compressed data structure representing the layout. While this technique does reduce the size of the layout data structure, it is a complex process requiring intensive computer power.
Therefore there is a need for a method and apparatus for reducing the size of a layout data structure without significantly impacting the quality or functionality of the layout data, and without the need for complex and computationally intensive operations.